Buffer memory for temporary storage of packet data has to accommodate high traffic rates with a wide range of packet sizes. The traditional techniques for dealing with such packet data is to pre-allocate the maximum buffer size for all traffic. In systems with large amounts of memory available this is the most economic solution, but it implies external hardware, memory chips and memory controllers. It also implies large bus interfaces to the external hardware and larger propagation delays through pin electronics. Thus, integrated circuit chips using traditional approaches have very high pin counts and chips sets with large pin counts also have complex wiring requirements for printed circuit boards.
A number of memory management techniques for buffer memory have been implemented. For example, memory allocation tables are typically managed in software by a processor, usually running with an operating system that provides for the allocation and de-allocation of memory. For example, the operations of malloc( ) and free( ) are standard ‘C’ function calls. However, the calls can not de-allocate part of an allocation, only the whole of an allocation.
Furthermore, traditional techniques for dealing with memory fragmentation are only partially effective. Most operating systems contain routines that can traverse the lists of allocated and de-allocated memory, and consolidate the de-allocated lists into fewer, larger chunks. However, all software controlled memory allocations takes longer to process because of the serial nature of the processor's instruction stream, and the complexity in most modern operating systems.
Most hardware controlled memory management units maintain allocation tables in main memory, and use memory allocation caches that contain associative look-up tables. These work very well, except that the caches are of limited size. When a cache miss occurs, the bus transfer must be trapped in mid cycle, and the missing cache entries must be loaded from the allocation tables in memory. All of this adds to the complexity of the hardware and software.
Most memory control hardware or software cannot return portions of unused memory back into the memory pool. In order to accomplish this, another allocation of the correct size is required, followed by a memory to memory copy of the data from the larger allocation to the smaller allocation. Then the larger allocation can be completely returned back to the memory pool. This process has undesirable overheads (memory to memory copy, and additional memory allocation).
It is therefore desirable to provide a buffer memory, which addresses, in part, some of the shortcomings of providing buffer memory noted above.